1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacture, and particularly, the present invention relates to a semiconductor device having memory cells and peripheral circuits which control the memory cells, and to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Semiconductor devices have been rapidly developing in which memory cells and peripheral circuits controlling the memory cells are formed in the same semiconductor substrate. Particularly, significant developments have been made in the area of systematic semiconductor devices which include a function of a semiconductor memory circuit, such as a dynamic random access memory (DRAM) and a function of a logic circuit.
Metal oxide semiconductor (MOS) transistors of such logic circuit have been employed to improve the driving ability of an electric current. Silicide layers are formed on gate electrodes, source regions and drain regions of the MOS transistors using a Self-Aligned Silicide (Salicide) method. Thereby, a resistance of the gate electrode and the source and drain regions is reduced and the logic circuit is capable of a high speed operation is.
Also, MOS transistors of the memory cells, particularly of the DRAM, must be capable of required to realize a high speed operation in order to transfer large amounts of data, such as image data. To realize such a high speed operation, it has been proposed to form silicide layers on the gate electrodes, source regions and drain regions of MOS transistors in the memory cells.
However, in the MOS transistor of the memory cells of the DRAM, concentrations of impurities in the source regions and the drain regions are set to low levels to restrain a short channel effect, to slacken a concentration of an electrical field in the drain region and to maintain a retention time. Therefore, junctions between the source regions or the drain regions and the semiconductor substrate are formed in the vicinity of a surface of the semiconductor substrate.
Consequently, if the silicide layers are formed on the gate electrodes, source regions and the drain regions of the MOS transistors in the memory cells of the DRAM, a high speed operation could be realized, but leak current from the source and drain regions to the semiconductor substrate would increase.
The silicide layers of the MOS transistors of the memory cells are simultaneously formed in the same step of forming the silicide layers of the MOS transistors of the peripheral circuits. Here, a method of forming an insulating layer, such as a nitride layer on the MOS transistors of the memory cells can be considered so as to avoid formation of the silicide layer on the MOS transistors of the memory cells. So, as it is impossible to form the silicide layers on the gate electrodes of the MOS transistors of the memory cells, an access time of the memory cells may be increased. Therefore, it is difficult to realize a high speed operation of the DRAM.